1. Field
Embodiments of the present invention relate to signal processing and, in particular, to digital signal processing.
2. Discussion of Related Art
As semiconductor technology is scaled, process variation becomes an ever-increasing problem. Even in the 90 nm node, threshold variance alone has become a significant factor. Designs meeting the worst-case process corner incur a 100% increase in energy per computation or a 25% performance penalty at the same energy consumption versus designs meeting the typical case. T. C. Chen, “Where CMOS is going: trendy hype vs. real technology,” ISSCC, 2006 IEEE Int. Conference Digest of Technical Papers, pp. 1-18, February 2006 discusses this. With larger process variations, design for the worst-case incurs an unacceptably high penalty. Relaxing the requirement for 100% correctness can significantly reduce these penalties.
Process variation may be defined rather broadly as any effect that may cause the transistor speed to vary. These include manufacturing effects, voltage and temperature fluctuations, and device degradation over the product lifetime. Of these, only manufacturing process effects are constant for a given chip, while the others are time-varying. In addition, voltage fluctuations are defined rather broadly to include voltage supply noise as well as intentional voltage scaling and voltage over scaling to save power consumption. The notion of voltage over scaling, intentionally scaling the voltage lower than that required for correct operation, was described in R. Hegde and N. R. Shanbhag, “Soft digital signal processing,” IEEE Trans. VLSI, vol. 9, pp. 813-823, December 2001.
Many applications (wireless communication, audio and video sigal processing, graphics, data mining, etc.) can tolerate some degree of error. The challenges and opportunities for error-tolerant design were laid out in M. A. Breuer, S. K. Gupta and T. M. Mak, “Defect and error tolerance in the presence of massive numbers of defects,” IEEE Design & Test of Computers, vol. 21 pp, 216-227, May-June 2004. The key challenge is ensuring that any errors due to process variation cause small changes in the final system output. For instance wireless communication devices are inherently designed with robustness to noise. As long as the aggregate system noise does not exceed some noise margin, the system will meet the quality of service goals. Noise margin is comprised of noise in the channel, analog front-end circuit noise, and digital sigal processing non-idealities, such as quantization noise.